Power Consumption During Current Regeneration Flow Through the Parasitic Diode of the Output Transistor:
Question: In the case regenerative current flows through the parasitic diode of the output MOSFET during PWM operation of the DC brush motor IC, the power consumption during regeneration is sometimes larger than the value obtained by multiplying the forward voltage of the parasitic diode by the motor current. Why is this?
Answer: When current flows as forward voltage is generated in the parasitic diode of the output MOSFET, the parasitic transistor operates and current flows from the power supply to ground. However, although this current is less than 1/10th the current flowing through the diode, when the power consumption becomes the Supply Voltage x Current between the Power Supply and Ground this value cannot be ignored if the power supply voltage is high.
In circuits when current is supplied by the DC brush motor during PWM drive, examples of regenerative current flowing through the parasitic diode when the output MOSFET is turned OFF are shown in Figure 1 below.
Figure 1. PWM Drive Equivalent Circuit Examples
(A) During Current Supply (B) Current Regeneration 1 (C) Current Regeneration 2
In the current supply circuit shown in (b) above, Q1 switches from ON to OFF, Q4 stays ON and current is regenerated through the parasitic diode in Q2, which is OFF, and Q4, which is ON.
In addition, during current regeneration in (c) above, Q1 and Q4 switch from ON to OFF, resulting in all MOSFETs being in the OFF state, and current flows through the parasitic diodes of Q2 and Q4.
Next we show the construction of an output MOSFET in a driver IC in Figure 2.
Figure 2. Output MOSFET Transistor Construction
In the output of an NMOS, a parasitic NPN transistor (Qa) is created from the N-type diffusion of the Drain (D), P-type diffusion used for device isolation, and N-type diffusion leading to the power supply (here connected to the output PMOS Source).
When regenerative current flows to the parasitic diode (Di_a) between the Source and Drain of the output NMOS, forward voltage is also generated between the diode between the Base and Emitter of the parasitic NPN transistor (Qa), since the P-type diffusion used for element isolation is connected to ground. Due to this, the parasitic NPN transistor Qa is turned ON and Collector current flows, drawing current from the power supply Ea.
In addition, a parasitic PNP transistor is formed from the P-type diffusion Drain (D), N-type diffusion Source and Back Gate, and P-type diffusion for the isolation layer in the output PMOS. When regenerative current flows to the parasitic diode (Di_b) between the output PMOS Source and Drain, the parasitic PNP transistor Qb turns ON and Collector current flows. Current flows to ground as well.
When regenerative current flows to the parasitic diode of the output MOS, due to this parasitic transistor the current flowing between the power supply and ground will be two magnitudes less than the regenerative current. But since this can differ greatly depending on LSI processes and chip layout, when performing current regeneration through the parasitic diode of the output MOS verification of the magnitude of current flowing based on this parasitic transistor is required.
For example, in Regenerative Current 2 in Figure 1 (c), with Ea=24V, Regenerative Current Io=1.0A, NMOS Parasitic Diode Forward Voltage VF_N=0.8V, PMOS Parasitic Diode Forward Voltage VF_P=0.95V, and a ratio of K1=1/100 with respect to the regenerative current flowing between the power supply and ground for both the NMOS and PMOS parasitic transistors, the power consumption Pc is determined by:
Pc＝Io×(VF_Ｎ＋VF_P＋2×k1×Ea)＝1×(0.8＋0.95＋2×1/100×24)＝1.75＋0.48＝2.23W
As we can see, the effects of power consumption due to current flowing through the parasitic transistors is large, making it an important consideration when the supply voltage is high.
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